Feitong Buke is seeking an experienced FPGA Engineer to develop and validate code for FPGAs in Redmond, WA. This role requires collaboration with electrical and firmware engineers and includes writing test benches for Verilog IPs. The ideal candidate will have at least 4 years of design experience in Verilog/System Verilog and familiarity with FPGA development tools. Comprehensive employee benefits and a competitive hourly rate of $70-$80/hr are offered. #J-18808-Ljbffr Feitong Buke
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